Z86E3016PSG Datasheet, PDF (113/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
95
shown in Figures 54 through 56. Port 2 is configured for input operation
on all bits and is set for open-drain (see Figure 55). If push-pull outputs
are required for Port 2 outputs, remember to configure them using P3M.
Please note that a WDT time-out from Stop-Mode Recovery does not do a
full reset. Certain registers that are not reset after Stop-Mode Recovery
will not be reset.
For the condition of the Ports after Stop-Mode Recovery, please refer to
specific device product specifications. In some cases, an Z8^® MCU fea-
tures the P01M, P2M, and P3M control register set back to the default
condition after reset while others do not.
All special I/O functions of Port 3 are inactive, with P33–P30 set as inputs
and P37–P34 set as outputs (see Figure 56).
Because the types and amounts of I/O vary greatly among the Z8^® CPU
family devices, the user is advised to review the selected device's product
specifications for the register default state after reset.
UM001602-0904
I/O Ports