Z86E3016PSG Datasheet, PDF (237/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
219
Table 39. Summary of Z8 Instruction Set
Instruction and
Operation
RLC dst
C
7
0
RR dst
C7
0
Address
Mode
dst src
Op Code
Byte
(Hex)
Flags Affected
C Z S VDH
R
10
[ [ [ [ ––
IR
11
R
E0 [ [ [ [ – –
IR
E1
RRC dst
R
C7
0
IR
C0 [ [ [ [ – –
C1
SBC dst, src
†
dst ← dst–src–C
3[ ] [ [ [ [ 1 [
SCF
C←1
DF 1 – – – – –
SRA dst
R
7
0
C
IR
D0 [ [ [ 0 – –
D1
SRP dst
RP ← src
Im
31
–– – – – –
STOP
6F – – – – – –
SUB dst, src
†
dst ← dst–src
2[ ] [ [ [ [ 1 [
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
UM001602-0904
Instruction Set