Z86E3016PSG Datasheet, PDF (315/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
297
Flag
C
Z
S
V
D
H
Description
Set if the bit rotated from the most significant bit position was 1
(i.e., bit 7 was 1).
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b (Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECh will be used as the
destination operand in the Op Code.
E
dst
Example
If the C Flag is reset and Register C6 contains 8Fh (10001111b), the
statement:
RLC C6
Op Code: 10 C6
leaves Register C6 with the value 1Eh (00011110b). The C and V Flags
are set, and S and Z flags are cleared.
Example
If the C Flag is reset, Working Register R4 contains C6h, and Register C6
contains 8Fh (10001111b), the statement:
RLC @R4
Op Code: 11 E4
leaves Register C6 with the value 1Eh (00011110b). The C and V Flags
are set, and S and Z flags are cleared.
UM001602-0904
Instruction Description