Z86E3016PSG Datasheet, PDF (176/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
158
Note: Internal clock scaling directly affects Counter/Timer operation—adjust-
ment of the prescaler and downcounter values may be required. To deter-
mine the actual HALT mode current (I_CC1) value for the various optional
modes available, see the related Z8 device’s product specification.
Stop Mode Operation
STOP mode provides the lowest possible device standby current. This
instruction turns off the on-chip oscillator and internal system clock.
To enter STOP mode, it is necessary to first flush the instruction pipeline
to avoid suspending execution in mid-instruction. To do this, the applica-
tion program must execute a NOP instruction (opcode = FFh) immedi-
ately before the STOP instruction (opcode = 6Fh), that is,
FF NOP ;clear the instruction pipeline
6F STOP ;enter STOP mode
STOP mode is exited by any one of the following resets: Power-On Reset
activation, WDT time out (if available), or a Stop-Mode Recovery source.
Upon reset generation, the processor will always restart the application
program at address 000Ch.
POR/RESET activation is present on all Z8 devices and is implemented as
a reset pin and/or an on-chip power on reset circuit.
Some Z8 devices allow for the on-chip WDT to run in STOP mode. If so
activated, the WDT time-out will generate a reset some fixed time period
after entering STOP mode.
Stop-Mode Recovery by the WDT will increase STOP mode standby cur-
rent (I_CC2). This is due to the WDT clock and divider circuitry that is now
enabled and running to support this recovery mode. See the product data
sheet for actual I_CC2 values.
Power-Down Modes
UM001602-0904