Z86E3016PSG Datasheet, PDF (190/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
172
facilitates break detection. For example, if a null character is received,
testing P30 results in a 0 being read.
Parity
The data format supported by the receiver must have a start bit, eight data
bits, and at least one stop bit. If parity is on, bit 7 of the data received will
be replaced by a Parity Error Flag. A parity error sets bit 7 to 1, otherwise,
bit D7 is set to 0. Figure 111 shows these data formats.
Received Data
(No Parity)
SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
One Stop Bit
Received Data
(With Parity)
SP P D6 D5 D4 D3 D2 D1 D0 ST
Figure 111. Receiver Data Formats
Start Bit
Seven Data Bits
Parity Error Flag
One Stop Bit
The Z8^® CPU hardware supports odd parity only, that is enabled by set-
ting the Port 3 Mode Register bit 7 to 1 (see Figure 112). If even parity is
required, PARITY mode should be disabled (P3M bit 7 set to 0), and soft-
ware must calculate the received data’s parity.
Serial Input/Output
UM001602-0904