Z86E3016PSG Datasheet, PDF (207/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
189
D4 set equal to 1 and D3 set equal to 0 to configure Port 1 as AD7–AD0.
Inputs and outputs are TTL-compatible. See Figure 123.
Reset. RESET (input, active Low) initializes the Z8^® CPU. When
RESET is deactivated, program execution begins from program location
000Ch. If held Low, RESET acts as a register file protect during power-
down and power-up sequences. To avoid asynchronous and noisy reset
problems, the Z8^® CPU is equipped with a reset filter of four external
clocks (4T_PC). If the external RESET signal is less than 4T_PC in duration,
no reset will occur. On the fifth clock after the RESET is detected, an
internal reset signal is latched and held for an internal register count of 18
or more external clocks, or for the duration of the external RESET, which-
ever is longer. Please refer to specific product specifications for length of
reset delay time.
Crystal1, Crystal2 (Oscillator Input and Output). These pins connect
a parallel-resonant crystal, ceramic resonator, LC, RC network, or exter-
nal single-phase clock to the on-chip oscillator input. Please refer to the
device product specifications for information on availability of RC oscil-
lator features.
External Addressing Configuration
The minimum bus configuration uses Port 1 as a multiplexed address/data
port (AD7–AD0), allowing access to 256 bytes of external memory. In
this configuration, the eight low-order bits (A0–A7) are multiplexed with
the data (D7–D0).
Port 0 can be programmed to provide either four additional address lines
(A11–A8), which increases the addressable memory to 4 KB, or eight
additional address lines (A15–A8), which increases the addressable exter-
nal memory up to 64 KB. It is required to add a NOP after configuring
Port 0/Port 1 for external addressing before jumping to external memory
execution.
UM001602-0904
External Interface