Z86E3016PSG Datasheet, PDF (142/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
124
Minimum duration is achieved by loading 01h (1 prescaler output count),
maximum duration is achieved by loading 00h (256 prescaler outputs
counts).
The prescaler and counter/timer are true divide-by-n counters.
T_OUT Modes
The Timer Mode Register TMR (F1h; see Figure 76), is used in conjunc-
tion with the Port 3 Mode Register P3M (F7h; see Figure 77) to configure
P36 for T_OUT operation for T0 and T1. In order for T_OUT to function, P36
must be defined as an output line by setting P3M bit 5 to 0. Output is con-
trolled by one of the counter/timers (T0 or T1) or the internal clock.
Register F1hR
Timer Mode Register (TMR)
(Read/Write)
D7 D6
D3
D0
0 = No Function
1 = Load T₀
0 = Disable T₁ Count
1 = Enable T₁ Count
T_OUT Modes:
T_OUT OFF = 00
T₀ OUT = 01
T₁ OUT = 10
Internal Clock OUT = 11
Figure 76. Timer Mode Register (T_OUT Operation)
Counters and Timers
UM001602-0904