Z86E3016PSG Datasheet, PDF (216/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
198
Register F8h (P01M)
Port 0–1 Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
External Memory Timing
0 = Normal
1 = Extended
Figure 130. Extended Bus Timing
Instruction Timing
The High throughput of the Z8^® CPU is due, in part, to the use of an
instruction pipeline, in which the instruction fetch and execution cycles
are overlapped. During the execution of the current instruction, the
opcode of the next instruction is fetched. Instruction pipelining is illus-
trated in Figure 131.
Figures 131 and 132 show typical instruction cycle timing for instructions
fetched from memory. For those instructions that require execution time
longer than that of the overlapped fetch, or reference program or data
memory as part of their execution, the pipe must be flushed.
Figures 131 and 132 assume the XTAL ÷ 2 clock mode is selected.
External Interface
UM001602-0904