Z86E3016PSG Datasheet, PDF (134/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
116
OSC
D1 (SMR)
÷2
Write
PRE0
Initial Value
Register
Internal Data Bus
Write
Read
T0
Initial Value
Register
T0
Current Value
Register
D0 (SMR)
÷4
÷16
Internal
Clock
Clock ^{External Clock}
Logic
÷4
T_IN P31
Internal Clock
Gated Clock
Triggered Clock
6-Bit
Down
Counter
6-Bit
Down
Counter
8-Bit
Down
Counter
8-Bit
Down
Counter
IRQ₄
÷2
T_OUT
P36
IRQ₅
PRE1
Initial Value
Register
Write
T1
Initial Value
Register
T1
Current Value
Register
Write
Read
Internal Data Bus
Figure 68. Counter/Timer Block Diagram
Counter/timers 0 and 1 are driven by a timer clock generated by dividing
the internal clock by four. The divide-by-four stage, the 6-bit prescaler,
and the 8-bit counter/timer form a synchronous 16-bit divide chain.
Counter/timer 1 can also be driven by a external input (T_IN) using P31.
Port 3 line P36 can serve as a timer output (T_OUT) through which T0, T1,
or the internal clock can be output. The timer output will toggle at the
end-of-count.
The counter/timer, prescaler, and associated mode registers are mapped
into the register file as shown in Figure 69. This allows the software to
Counters and Timers
UM001602-0904