Z86E3016PSG Datasheet, PDF (175/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
157
Power-Down Modes
In addition to the standard RUN mode, the Z8^® CPU supports two Power-
Down modes to minimize device current consumption. The two modes
supported are HALT and STOP.
Halt Mode Operation
HALT mode suspends instruction execution and turns off the internal
CPU clock. The on-chip oscillator circuit remains active so the internal
clock continues to run and is applied to the Counter/Timer(s) and inter-
rupt logic.
To enter HALT mode, it is necessary to first flush the instruction pipeline
to avoid suspending execution in mid-instruction. To do this, the applica-
tion program must execute a NOP instruction (opcode = FFh) immedi-
ately before the HALT instruction (opcode 7Fh), that is:
FF NOP ;clear the instruction pipeline
7F HALT ;enter HALT mode
HALT mode is exited by interrupts, either externally or internally gener-
ated. Upon completion of the interrupt service routine, the user program
continues from the instruction after HALT.
HALT mode may also be exited via a POR/RESET activation or a Watch–
Dog Timer (WDT) time-out. (See the product data sheet for WDT avail-
ability). In this case, program execution will restart at the reset restart
address 000Ch.
To further reduce power consumption in HALT mode, some Z8 family
devices allow dynamic internal clock scaling. Clock scaling may be
accomplished on the fly by reprogramming bit 0 and/or bit1 of the Stop-
Mode Recovery register (SMR). See Figure 103 on page 160.
UM001602-0904
Power-Down Modes