Z86E3016PSG Datasheet, PDF (218/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
200
Clock
A15–A8
A7–A0
AS
M1
M2
M3
T1
T2
T3
T1
T2
T3
T1
T2
T3
A15–A8
A7–A0
A7–A0
A15–A8
A7–A0
A7–A0
A15–A8
A7–A0
A7–A0
DS
R/W
Fetch 1st Byte
Fetch 2nd Byte
Fetch 3rd Byte
(3-Byte Instruction)
Fetch 1st Byte (1- or 2-Byte Instruction)
*Port inputs are strobed during T2, which is two internal system clocks before
the execution cycle of the current instruction.
Figure 132. Instruction Cycle Timing (2- and 3-Byte Instructions)
Z8 Reset Conditions
After a hardware reset, extended timing is set to accommodate slow mem-
ory access during the configuration routine, DM is inactive, the stack
resides in the register file. Port 0, 1, and 2 are reset to input mode. Port 2
is set to Open-Drain Mode.
External Interface
UM001602-0904