Z86E3016PSG Datasheet, PDF (191/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
173
Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
0 = Parity OFF
1 = Parity ON
Figure 112. Port 3 Mode Register Parity
Transmitter Operation
The transmitter consists of a transmitter buffer (SIO Register [F0h]), a
parity generator, and associated control logic. The transmitter block dia-
gram is shown as part of Figure 105 on page 165.
After a hardware reset or after a character has been transmitted, the trans-
mitter is forced to a marking state (output always High) until a character
is loaded into the transmitter buffer, SIO Register (F0h). The transmitter
is loaded by specifying the SIO Register as the destination register of any
instruction.
T0’s output drives a divide-by-16 counter that in turn generates a shift
clock every 16 counts. This counter is reset when the transmitter buffer is
written by an instruction. This reset synchronizes the shift clock to the
software. The transmitter then outputs one bit per shift clock, through Port
3 bit 7, until a start bit, the character written to the buffer, and two stop
bits have been transmitted. After the second stop bit has been transmitted,
the output is again forced to a marking state. Interrupt request IRQ4 is
generated at this time to notify the processor that the transmitter is ready
to accept another character.
UM001602-0904
Serial Input/Output