Z86E3016PSG Datasheet, PDF (188/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
170
UART Receiver Operation
The receiver consists of a receiver buffer (SIO Register [F0h]), a serial-in,
parallel-out shift register, parity checking, and data synchronizing logic.
The receiver block diagram is shown as part of Figure 105 on page 165.
Receiver Shift Register
After a hardware reset or after a character has been received, the Receiver
Shift Register is initialized to all 1s and the shift clock is stopped. Serial
data, input through Port 3 bit 0, is synchronized to the internal clock by
two D-type flip-flops before being input to the Shift Register and the start
bit detection circuitry.
The start bit detection circuitry monitors the incoming data stream, look-
ing for a start bit (a High-to-Low input transition). When a start bit is
detected, the shift clock logic is enabled. The T0 input is divided-by-16
and, when the count equals eight, the divider outputs a shift clock. This
clock shifts the start bit into the Receiver Shift Register at the center of
the bit time. Before the shift actually occurs, the input is rechecked to
ensure that the start bit is valid. If the detected start bit is false, the
receiver is reset and the process of looking for a start bit is repeated. If the
start bit is valid, the data is shifted into the Shift Register every sixteen
counts until a full character is assembled (see Figure 110).
Serial Input/Output
UM001602-0904