Z86E3016PSG Datasheet, PDF (73/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
55
Watch–Dog Timer
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets
the Z8^® CPU if it reaches its terminal count. When operating in the RUN
or HALT modes, a WDT reset is functionally equivalent to a hardware
POR reset. The WDT is initially enabled by executing the WDT instruc-
tion and refreshed on subsequent executions of the WDT instruction. The
WDT cannot be disabled after it has been initially enabled. Permanently
enabled WDTs are always enabled and the WDT instruction is used to
refresh it. The WDT circuit is driven by an on-board RC oscillator or
external oscillator from the XTAL1 pin. The POR clock source is selected
with bit 4 of the Watch–Dog Timer Mode register (WDTMR). In some
cases, a Z8 that offers the WDT but does not have a WDTMR register, has
a fixed WDT time-out and uses the on board RC oscillator as the only
clock source. Please refer to specific product specifications for selectabil-
ity of time-out, WDT during HALT and STOP modes, source of WDT
clock, and availability of the permanently-on WDT option.
Execution of the WDT instruction affects the Z (zero), S (sign), and V
(overflow) flags.
UM001602-0904
Watch–Dog Timer