Z86E3016PSG Datasheet, PDF (184/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
166
Configuration of the UART is controlled by the Port 3 Mode Register
(P3M) located at address F7h. the Z8^® CPU always transmits eight bits
between the start and stop bits (eight Data Bits or seven Data Bits and one
Parity Bit). Odd parity generation and detection is supported.
The SIO Register and its associated Mode Control Registers are mapped
into the Standard Z8 Register File as shown in Table 23. The organization
allows the software to access the UART as general-purpose registers,
eliminating the requirement for special instructions.
Table 23. UART Register Map
Register Name
Port 3 Mode
T0 Prescaler
Timer/Counter0
Timer Mode
UART
Identifier
P3M
PRE0
T0
TMR
SIO
Hex Address
F7
F5
F4
F1
F0
UART Bit-Rate Generation
When Port 3 Mode Register bit 6 is set to 1, the UART is enabled and T0
automatically becomes the bit rate generator (see Figure 106). The end-
of-count signal of T0 no longer generates Interrupt Request IRQ4.
Instead, the signal is used as the input to the divide-by-16 counters (one
each for the receiver and the transmitter) that clock the data stream.
Serial Input/Output
UM001602-0904