Z86E3016PSG Datasheet, PDF (211/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
193
Clock
Machine Cycle
T1
T2*
T3
A15-A8
AD7–AD0
A7–A0
A8-A15
D7–D0 IN
AS
DS
R/W
DM
Read Cycle
*Port inputs are strobed during T2, which is two internal systems clocks
before the execution cycle of the current instruction.
Figure 126. External Instruction Fetch or Memory Read Cycle
UM001602-0904
External Interface