Z86E3016PSG Datasheet, PDF (51/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
33
Clock
The Z8^® CPU derives its timing from on-board clock circuitry connected
to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a
divide-by-two shaping circuit, and a clock buffer. Figure 12 illustrates the
clock circuitry. The oscillator’s input is XTAL1 and its output is XTAL2.
The clock can be driven by a crystal, a ceramic resonator, LC clock, RC,
or an external clock source.
Frequency Control
In some cases, the Z8^® CPU has an EPROM/OTP option or a Mask ROM
option bit to bypass the divide-by-two flip flop in Figure 12. This feature
is used in conjunction with the low EMI option. When low EMI is
selected, the device output drive and oscillator drive is reduced to approx-
imately 25 percent of the standard drive and the divide-by-two flip flop is
bypassed such that the XTAL clock frequency is equal to the internal sys-
tem clock frequency. In this mode, the maximum frequency of the XTAL
clock is 4 MHz. Please refer to specific product specification for availabil-
ity of options and output drive characteristics.
XTAL1
XTAL2
OSC
÷2
Figure 12. Z8^® CPU Clock Circuit
Buffer
Internal
Clock
Clock Control
In some cases, the Z8^® CPU offers software control of the internal system
clock via programming register bits. The bits are located in the Stop-
Mode Recovery Register in Expanded Register File Bank F, Register 0Bh.
UM001602-0904
Clock