Z86E3016PSG Datasheet, PDF (163/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
145
Table 19. Interrupt Priority (Continued)
Group
A
Bit
Bit 5
Value
0
1
Priority
Highest
IRQ5
IRQ3
Lowest
IRQ3
IRQ5
Table 20. Interrupt Group Priority
Bit Pattern
Bit 4
0
0
0
0
1
1
1
1
Bit 3
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
Group Priority
High
Not Used
C
A
A
B
C
B
Not Used
Medium
A
B
C
C
B
A
Low
B
C
B
A
A
C
Interrupt Mask Register Initialization
The Interrupt Mask Register individually or globally enables or disables
the six interrupt requests (see Figure 97). When bit 0 to bit 5 are set to 1,
the corresponding interrupt requests are enabled. Bit 7 is the master
enable and must be set before any of the individual interrupt requests can
be recognized. Resetting bit 7 globally disables all of the interrupt
requests. Bit 7 is set and reset by the EI and DI instructions. It is automat-
UM001602-0904
Interrupts