Z86E3016PSG Datasheet, PDF (251/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
233
Address mode IRR can be used to specify a 4-bit Working Register Pair. In
Note: _{this format, the destination Working Register Pair operand is specified by}
adding 1110b (Eh) to the high nibble of the operand. For example, if
Working Register Pair RR12 (CH) is the destination operand, then ECh
will be used as the destination operand in the Op Code.
E
src
or
E
dst
Example
If the contents of the PC are 1A47h and the contents of the SP (Registers
FEh and FFh) are 3002h, the statement:
CALL 3521h
Op Code: D6 35 21
causes the SP to be decremented to 3000h, 1A4Ah (the address following
the CALL instruction) to be stored in external data memory 3000 and
3001h, and the PC to be loaded with 3521h. The PC now points to the
address of the first statement in the procedure to be executed.
Example
If the contents of the PC are 1A47h, the contents of the SP (Register FFh)
are 72h, the contents of Register A4h are 34h, and the contents of Regis-
ter Pair 34h are 3521h, the statement:
CALL @A4h
Op Code: D4 A4
causes the SP to be decremented to 70h, 1A4Ah (the address following
the CALL instruction) to be stored in R70h and 71h, and the PC to be
loaded with 3521h. The PC now points to the address of the first state-
ment in the procedure to be executed.
UM001602-0904
Instruction Description