Z86E3016PSG Datasheet, PDF (32/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
14
• When register FDh (Register Pointer) is read, the least significant four
bits (lower nibble) will indicate the current Expanded Register File
Bank. (Example: 0000 indicates the Standard Register File, while
1010 indicates Expanded Register File Bank A.)
• When Ports 0 and 1 are defined as address outputs, registers 00h and
01h will return 1s in each address bit location when read.
• Writing to bits that are defined as timer output, serial output, or hand-
shake output will have no effect.
• The Z8^® CPU instruction DJNZ uses any general-purpose working
register as a counter.
• Logical instructions such as OR and AND require that the current
contents of the operand be read. They therefore will not function
properly on write-only registers.
• The WDTMR register must be written within the first 60 internal sys-
tem clocks (SCLK) of operation after a reset.
Z8 Expanded Register File
The standard register file of the Z8^® CPU has been expanded to form 16
Expanded Register File (ERF) Banks, as shown in Figure 6. Each ERF
Bank consists of up to 256 registers (the same amount as in the Standard
Register File) that can then be divided into 16 Working Register Groups.
This expansion allows for access to additional feature/peripheral control
and data registers.
Address Space
UM001602-0904