Z86E3016PSG Datasheet, PDF (179/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
161
The SMR register is available in select Z8 CPU products. Refer to the
device product specification to determine SMR options available.
SCLK ÷ TCLK Divide-by-16 Select. This D0 bit of the SMR controls a
divide-by-16 prescaler of SCLK ÷ TCLK. The purpose of this control is
to selectively reduce device power consumption during normal processor
execution (SCLK control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic).
External Clock Divide-by-Two. This D1 bit can eliminate the oscillator
divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and
Timer Clock (TCLK) are equal to the external clock frequency divided by
two. The SCLK ÷ TCLK is equal to the external clock frequency when
this bit is set (D1 = 1). Using this bit together with D7 of PCON helps fur-
ther lower EMI (D7 (PCON) = 0, D1 (SMR) = 1). The default setting is
zero.
Stop-Mode Recovery Source. The D2, D3, and D4 bits of the SMR
specify the wake-up source of the stop-recovery and (Table 22 and
Figure 104).
Table 22. Stop-Mode Recovery Source
SMR: 432
D4 D3 D2 Description of Operation
0 0 0 POR and/or external reset recovery.
0 0 1 P30 transition.
0 1 0 P31 transition (not in Analog Mode).
0 1 1 P32 transition (not in Analog Mode).
1 0 0 P33 transition (not in Analog Mode).
UM001602-0904
Power-Down Modes