Z86E3016PSG Datasheet, PDF (178/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
160
Stop-Mode Recovery Register
This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (see Figure 103). All bits are Write-Only, except bit
7, that is Read-Only. Bit 7 is a flag bit that is hardware set on the condi-
tion of stop-recovery and reset by a power-on cycle. Bit 6 controls
whether a low level or a high level is required from the recovery source.
Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, of the SMR
register, specify the source of the Stop-Mode Recovery signal. Bits 0 and
1 control internal clock divider circuitry. The SMR is located in Bank F of
the Expanded Register File at address 0Bh.
SMR (Fh) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK ÷ TCLK Divide-by-16
0 OFF **
1 ON
External Clock Divide by 2
0 SCLK ÷ TCLK = XTAL ÷ 2*
1 SCLK ÷ TCLK = XTAL
Stop-Mode Recovery Source
000 POR Only and/or External Reset
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0–3
111 P2 NOR 0–7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read Only)
0 POR*
1 Stop Recovery
* Default setting after RESET.
** Default setting after RESET and Stop-Mode Recovery.
Figure 103. Stop-Mode Recovery Register (Write-Only Except Bit D7,
Which Is Read-Only)
Power-Down Modes
UM001602-0904