Z86E3016PSG Datasheet, PDF (195/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
177
Table 25. SPI Pin Configuration
Name
DI
DO
SS
SK
Function
Data-In
Data-Out
Slave Select
SPI Clock
Pin Location
P20
P27
P35
P34
The SPI Control Register (SCON; see Figure 116), is a read/write register
that controls Master/Slave selection, interrupts, clock source and phase
selection, and error flag. Bit 0 enables/disables the SPI with the default
being SPI disabled. A 1 in this location will enable the SPI, and a 0 will
disable the SPI. Bits 1 and 2 of the SCON register in Master Mode select
the clock rate. The user may choose whether internal clock is divide-by-2,
4, 8, or 16. In Slave Mode, Bit 1 of this register flags the user if an overrun
of the RxBUF Register has occurred. The RxCharOverrun flag is only
reset by writing a 0 to this bit. In slave mode, bit 2 of the Control Register
disables the data-out I/O function. If a 1 is written to this bit, the data-out
pin is released to its original port configuration. If a 0 is written to this bit,
the SPI shifts out one bit for each bit received. Bit 3 of the SCON Register
enables the compare feature of the SPI, with the default being disabled.
When the compare feature is enabled, a comparison of the value in the
SCOMP Register is made with the value in the RxBUF Register. Bit 4 sig-
nals that a receive character is available in the RxBUF Register.
UM001602-0904
Serial Input/Output