Z86E3016PSG Datasheet, PDF (81/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
63
and can then be read. This mechanism allows the user to initialize the out-
puts prior to driving their loads (see Figure 29).
Because port inputs are asynchronous to the Z8^® CPU internal clock, a
READ operation could occur during an input transition. In this case, the
logic level might be uncertain (somewhere between a logic 1 and 0). To
eliminate this meta-stable condition, the Z8^® CPU latches the input data
two clock periods prior to the execution of the current instruction. The
input register uses these two clock periods to stabilize to a legitimate logic
level before the instruction reads the data.
Note: The following sections describe the generic function of the Z8^® CPU
ports. Any additional features of the ports such as SPI, C/T, and Stop-
Mode Recovery are covered in their own section.
Port 0
This section deals with only the I/O operation of Port 0. The port's exter-
nal memory interface operation is covered later in this manual. Figure 29
shows a block diagram of Port 0. This diagram also applies to Ports 1 and
2.
UM001602-0904
I/O Ports