Z86E3016PSG Datasheet, PDF (267/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
249
Decrement Word
DECW dst
Instruction Format
OPC
dst
Cycles
10
10
OPC
(Hex)
80
81
Address Mode
dst
RR
IR
Operation
dst ← dst–1
The contents of the destination (which must be an even address) operand
are decremented by one. The destination operand can be a Register Pair or
a Working Register Pair.
Flag
C
Z
S
V
D
H
Description
Unaffected
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set (negative); cleared otherwise
Set if arithmetic overflow occurs; cleared otherwise
Unaffected
Unaffected
Note: Address modes RR or IR can be used to specify a 4-bit Working Register
Pair. In this format, the destination Working Register Pair operand is spec-
ified by adding 1110b (Eh) to the high nibble of the operand. For example,
if Working Register Pair R12 (CH) is the destination operand, then ECh
will be used as the destination operand in the Op Code.
E
dst
Example
If Register Pair 30h and 31h contain the value 0AF2h, the statement:
UM001602-0904
Instruction Description