Z86E3016PSG Datasheet, PDF (189/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
171
(R)
RCVR
Data
Start Bit Transition Detected
Stop Bit
One or More
Shift
Clock
Eight T0 Counts Later Shifting Starts
RCVR
IRQ3
Figure 110. Receiver Timing
Shift register Contents
Transferred to Receive Buffer
and IRQ3 is Generated
After a full character has been assembled in the receiver’s buffer, SIO
Register (F0h), Interrupt Request IRQ3 is generated. The shift clock is
stopped and the Shift Register reset to all 1s. The start bit detection cir-
cuitry begins monitoring the data input for the next start bit. This cycle
allows the receiver to synchronize on the center of the bit time for each
incoming character.
Overwrites
Although the receiver is single buffered, it is not protected from being
overwritten, so the software must read the SIO Register (F0h) within one
character time after the interrupt request (IRQ3). the Z8^® CPU does not
have a flag to indicate this overrun condition. If polling is used, the IRQ3
bit in the Interrupt Request Register must be reset by software.
Framing Errors
Framing error detection is not supported by the receiver hardware, but by
responding to the interrupt request within one character bit time, the soft-
ware can test for a stop bit on P30. Port 3 bits are always readable, which
UM001602-0904
Serial Input/Output