Z86E3016PSG Datasheet, PDF (164/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
146
ically reset during an interrupt service routine and set following the exe-
cution of an Interrupt Return (IRET) instruction.
Bit 7 must be reset by the DI instruction before the contents of the Inter-
rupt Mask Register or the Interrupt Priority Register are changed except:
• Immediately after a hardware reset
• Immediately after executing an interrupt service routine and before
IMR bit 7 has been set by any instruction
Register FBh
Interrupt Request Register (IMR)
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
0 = Disables IRQ0
1 = Enables IRQ0
0 = Disables IRQ1
1 = Enables IRQ1
0 = Disables IRQ2
1 = Enables IRQ2
0 = Disables IRQ3
1 = Enables IRQ3
0 = Disables IRQ4
1 = Enables IRQ4
0 = Disables IRQ5
1 = Enables IRQ5
0 = Disables RAM Protect
1 = Enables RAM Protect
0 = Disables Interrupt
1 = Enables Interrupt
Figure 97. Interrupt Mask Register
Interrupts
UM001602-0904