Z86E3016PSG Datasheet, PDF (235/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
217
Table 39. Summary of Z8 Instruction Set
Instruction and
Operation
Address
Mode
dst src
Op Code
Byte
(Hex)
Flags Affected
C Z S VDH
dst ← src
rR
r8
Rr
r9
r = 0–F
rX
C7
Xr
D7
r Ir
E3
Ir r
F3
RR
E4
R IR
E5
R IM E 6
IR IM E 7
IR R
F5
LDC dst, src
r Irr
C2 – – – – – –
dst ← src
lrr r
D2
LDCI dst, src
Ir Irr
C3 – – – – – –
dst ← src
r ← r + 1 or
rr ←rr + 1
lrr Ir
D3
LDE dst, src
r Irr
82 – – – – – –
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
UM001602-0904
Instruction Set