Z86E3016PSG Datasheet, PDF (206/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
188
Pin Descriptions
The following sections briefly describe the pins associated with the Z8^®
CPU external memory interface.
Address Strobe (output, active Low). Address Strobe (AS) is pulsed
Low once at the beginning of each machine cycle. The rising edge of AS
indicates the address, Read/Write (R/W), and data memory (DM) signals
are valid for program or data memory transfers. In some cases, the Z8^®
CPU address strobe is pulsed low regardless of accessing external or
internal memory. Please refer to specific product specifications for AS
operation.
Data Strobe (Output, Active Low). Data Strobe (DS) provides the tim-
ing for data movement to or from the Address/Data bus for each external
memory transfer. During a Write Cycle, data out is valid at the leading
edge of the DS. During a Read Cycle, data in must be valid prior to the
trailing edge of the DS.
Read/Write (Output). Read/Write (R/W) determines the direction of
data transfer for memory transactions. R/W is Low when writing to pro-
gram or data memory, and High for all other transactions.
Data Memory (Output). Data memory (DM) provides a signal to sepa-
rate external program memory from external data memory. It is a pro-
grammable function on pin P34. Data memory is active low for external
data memory accesses and high for external program memory accesses.
High Address Lines A15–A8. A15–A8 provide the High Address lines
for the memory interface. The Port 0–1 mode registers must have bits D7
and D1 set equal to 1 to configure Port 0 as A15–A8. Outputs can be
CMOS- or TTL-compatible. Please refer to product specifications for
actual type. See Figure 123.
Address/Data Lines AD7–AD0. AD7–AD0 is a multiplexed Address/
Data memory interface. The lower eight Address lines (A7–A0) are multi-
plexed with Data lines (D7–D0). Port 0–1 mode registers must have bits
External Interface
UM001602-0904