Z86E3016PSG Datasheet, PDF (167/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
149
Table 21. IRQ Register Configuration*
IRQ
Interrupt Edge
D7
D6
P31
0
0
F
0
1
F
1
0
R
1
1
R/F
*Note: F = Falling Edge; R = Rising Edge.
P32
F
R
F
R/F
The proper sequence for programming the interrupt edge select bits is
(assumes IPR and IMR have been previously initialized).
DI
;Inhibit all interrupts until input edges are
configured.
OR IRQ,#XX 000000b ;Configure interrupt; do not disturb edges
as required—IRQ 0-5.
EI
;Reenable interrupts.
El Instruction
Interrupt Request Register
(IRQ, FAh)
S
RESET
R
POR
Figure 99. IRQ Reset Functional Logic Diagram
UM001602-0904
Interrupts