Z86E3016PSG Datasheet, PDF (138/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
120
Counter/Timer Operation
Under software control, counter/timers are started and stopped via the
Timer Mode Register (TMR,F1h) bits D0–D3 (see Figure 73). Each
counter/timer is associated with a Load bit and an Enable Count bit.
Load and Enable Count Bits
Setting the Load bit (D0 for T0 and D2 for T1) transfers the initial value
in the prescaler and the counter/timer registers into their respective down-
counters. The next internal clock resets bits D0 and D2 to 0, readying the
Load bit for the next load operation. New values may be loaded into the
down-counters at any time. If the counter/timer is running, it continues to
do so and starts the count over with the new value. Therefore, the Load bit
actually functions as a software re-trigger.
R241 TMR
Timer Mode Register
(% F1; Read/Write)
D3 D2 D1 D0
0 = No Function
1 = Load T₀
0 = Disable T₀ Count
1 = Enable T₀ Count
0 = No Function
1 = Load T₁
0 = Disable T₁ Count
1 = Enable T₁ Count
Figure 73. Timer Mode Register
The counter timers remain at rest as long as the Enable Count bits are 0.
To enable counting, the Enable Count bit (D₁ for T0 and D₃ for T1) must
Counters and Timers
UM001602-0904