Z86E3016PSG Datasheet, PDF (86/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
68
under handshake control return data latched into the input register via the
input strobe.
The Port 0–1 Mode resistor bits D1–D0 and D7–D6 are used to configure
Port 0 nibbles. The lower nibble (P00–P03) can be defined as inputs by
setting bits D1 to 0 and D0 to 1, or as outputs by setting both D1 and D0
to 0. Likewise, the upper nibble (P04–P07) can be defined as inputs by
setting bits D7 to 0 and D6 to 1, or as outputs by setting both D6 and D7
to 0 (see Figure 32).
Handshake Operation
When used as an I/0 port, Port 0 can be placed under handshake control
by programming the Port 3 Mode register bit D2 to 1. In this configura-
tion, handshake control lines are DAV0 (P32) and RDY0 (P35) when Port
0 is an input port, or RDY0 (P32) and DAV0 (P35) when Port 0 is an out-
put port (see Figure 33).
Handshake direction is determined by the configuration (input or output)
assigned to the Port 0 upper nibble, P04–P07. The lower nibble must have
the same I/0 configuration as the upper nibble to be under handshake con-
trol. Figure 30 illustrates the Port 0 upper and lower nibbles and the asso-
ciated handshake lines of Port 3.
Port 1
This section deals only with the I/0 operation. The port's external memory
interface operation is discussed later in this manual. Figure 29 shows a
block diagram of Port 1.
General I/O Mode
Port 1 can be an 8-bit, bidirectional, CMOS or TTL compatible port with
multiplexed address (A7–A0) and data (D7–D0) ports. These eight I/O
lines can be byte programmed as inputs or outputs or can be configured
under software control as an Address/Data port for interfacing to external
I/O Ports
UM001602-0904