Z86E3016PSG Datasheet, PDF (159/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
141
PIN
D
(IRQ₃
Serial In)
Clock
Q
D
P3M₆
Q
IRQ₃ External Source
Serial Receiver
IRQ₃
Internal Source
IRQ₃
Figure 93. Interrupt Source IRQ3 Block Diagram
Internal Interrupt Sources
Internal sources involve interrupt requests IRQ0, IRQ2, IRQ3, IRQ4, and
IRQ5. Internal sources are ORed with the external sources, so either an
internal or external source can trigger the interrupt. Internal interrupt
sources and trigger conditions are device dependent.
See the device product specification to determine available sources, trig-
gering edge options, and exact programming details. For more details on
the internal interrupt sources, refer to the chapters describing the Counter/
Timer, I/O ports, and Serial I/O.
Interrupt Request Register Logic and Timing
Figure 94 shows the logic diagram for the Interrupt Request (IRQ) Regis-
ter. The leading edge of the request will set the first flip-flop, that will
remain set until interrupt requests are sampled.
Requests are sampled internally during the last clock cycle before an
opcode fetch (see Figure 95). External requests are sampled two internal
UM001602-0904
Interrupts