Z86E3016PSG Datasheet, PDF(143/348 Page) Zilog, Inc. – Z86E3016PSG

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Z86E3016PSG Datasheet, PDF (143/348 Pages) Zilog, Inc. – Z86E3016PSG

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Z8 CPU

User Manual

125

Register F7h

Port 3 Mode Register (P3M)

(Write-Only)

D7 D6 D5 D4 D3 D2 D1 D0

0 P31 = Input (TIN) P36 = Output (TOUT)

1 P31 = DAV2/RDY2 P36 = RDY2/DAV2

Figure 77. Port 3 Mode Register (TOUT Operation)

The counter/timer to be output is selected by TMR bit 7 and bit 6. T0 is

selected to drive the TOUT line by setting bit 7 to 0 and bit 6 to 1. Like-

wise, T1 is selected by setting bit 7 and bit 6 to 1 and 0, respectively. The

counter/timer TOUT mode is turned off by setting TMR bit and bit 6 both

to 0, freeing P36 to be a data output line.

TOUT is initialized to a logic 1 whenever the TMR Load bit (bit 0 for T0

or bit 1 for T2) is set to 1. The TOUT conï¬guration timer load, and Timer

Enable Count bits for the counter/timer driving the TOUT pin can be set at

the same time. For example, using the instruction:

OR TMR,#43h

â¢ Conï¬gures T0 to drive the TOUT pin (P36)

â¢ Sets the P36 TOUT pin to a logic 1 level

â¢ Loads the initial PRE0 and T0 levels into their respective counters

and starts the counter after the M2T2 machine state after the operand

is fetched

At end-of-count, the interrupt request line (IRQ4 or IRQ5), clocks a tog-

gle ï¬ip-ï¬op. The output of this ï¬ip-ï¬op drives the TOUT line, P36. In all

cases, when the selected counter/timer reaches its end-of-count, TOUT

toggles to its opposite state (see Figure 78). If, for example, the counter/

UM001602-0904

Counters and Timers

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