Z86E3016PSG Datasheet, PDF (158/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
140
The interrupt sources and trigger conditions are device dependent. See the
device product specification to determine available sources (internal and
external), triggering edge options, and exact programming details.
n = 2, 3, 1
Multiple Input
and Signal
P3_n
Conditioning
Circuitry
S
Q
D
Q
R
System Clock
(Internal)
IRQ_m
m = 0,1,2
D
Q
Figure 92. Interrupt Sources IRQ0-IRQ2 Block Diagram
When the Port 3 pin (P31, P32, or P33) transitions, the first flip-flop is set.
The next two flip-flops synchronize the request to the internal clock and
delay it by two internal clock periods. The output of the last flip-flop
(IRQ0, IRQ1, or IRQ2) goes to the corresponding Interrupt Request Reg-
ister.
IRQ3 can be generated from an external source only if Serial In is not
enabled. Otherwise, its source is internal. The external request is gener-
ated by a Low edge signal on P30 as shown in Figure 93. Again, the exter-
nal request is synchronized and delayed before reaching IRQ3. Some Z8
products replace P30 with P32 as the external source for IRQ3. In this
case, IRQ3 interrupt generation follows the logic as illustrated in
Figure 92.
Although interrupts are edge triggered, minimum interrupt request Low
and High times must be observed for proper operation. See the device
product specification for exact timing requirements on external interrupt
requests (T_WIL, T_WIH).
Interrupts
UM001602-0904