Z86E3016PSG Datasheet, PDF (180/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
162
Table 22. Stop-Mode Recovery Source
SMR: 432
D4 D3 D2 Description of Operation
1 0 1 P27 transition.
1 1 0 Logical NOR of P20 through P23.
1 1 1 Logical NOR of P20 through P27.
Stop-Mode Recovery Delay Select. This D5 bit, if High, enables the
T_POR RESET delay after Stop-Mode Recovery. The default configuration
of this bit is 1. If the fast wake up is selected, the Stop-Mode Recovery
source is kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select. A 1 in this D6 bit position indicates
that a high level on any one of the recovery sources wakes the Z8^® CPU
from STOP mode. A 0 indicates low-level recovery. The default is 0 on
POR (see Figure 104).
Cold or Warm Start. This D7 bit is set by the device upon entering
STOP mode. A 0 in this bit (cold) indicates that the device reset by POR/
WDT RESET. A 1 in this bit (warm) indicates that the device awakens by
a SMR source.
Power-Down Modes
UM001602-0904