Z86E3016PSG Datasheet, PDF (299/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
281
Logical OR
OR dst, src
Instruction Format
OPC
OPC
OPC
dst src
src
dst
Cycles
6
6
OPC
(Hex)
02
03
Address
Mode
dst src
r
r
r
lr
dst
10
04
R
R
10
05
R
IR
src
10
06
R
IM
10
07 IR IM
Operation
dst ← dst OR src
The source operand is logically ORed with the destination operand and
the result is stored in the destination operand. The contents of the source
operand are not affected. The OR operation results in a one bit being
stored whenever either of the corresponding bits in the two operands is a
one. Otherwise, a zero bit is stored.
Flag
C
Z
S
V
D
H
Description
Unaffected
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set; cleared otherwise
Always reset to 0
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
UM001602-0904
Instruction Description