Z86E3016PSG Datasheet, PDF (65/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
47
Reset
This section describes the Z8^® CPU reset conditions, reset timing, and
register initialization procedures. Reset is generated by Power-On Reset
(POR), Reset Pin, Watch–Dog Timer (WDT), and Stop-Mode Recovery.
A system reset overrides all other operating conditions and puts the Z8^®
CPU into a known state. To initialize the chip’s internal logic, the RESET
input must be held Low for at least 21 SCP or 5 XTAL clock cycles. The
control register and ports are reset to their default conditions after a POR,
a reset from the RESET pin, or Watch–Dog Timer time-out while in RUN
mode and HALT mode. The control registers and ports are not reset to
their default conditions after Stop- Mode Recovery and WDT time-out
while in STOP mode.
While RESET pin is Low, AS is output at the internal clock rate, DS is
forced Low, and R/W remains High. The program counter is loaded with
000Ch. I/O ports and control registers are configured to their default reset
state.
Resetting the Z8^® CPU does not affect the contents of the general-pur-
pose registers.
Reset Pin, Internal POR Operation
In some cases, the Z8^® CPU hardware RESET pin initializes the control
and peripheral registers, as shown in Tables 12 through 15. Specific reset
values are shown by 1 or 0, while bits whose states are unknown are indi-
cated by the letter U. Tables 12 through 15 show the reset conditions for
the Z8 CPU.
Note: The register file reset state is device dependent. Please refer to the selected
device product specifications for register availability and reset state.
UM001602-0904
Reset