Z86E3016PSG Datasheet, PDF (192/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
174
Overwrites
The user is not protected from overwriting the transmitter, so it is up to
the software to respond to IRQ4 appropriately. If polling is used, the
IRQ4 bit in the Interrupt Request Register must be reset.
Parity
The data format supported by the transmitter has a start bit, eight data
bits, and at least two stop bits. If parity is on, bit 7 of the data transmitted
will be replaced by an odd parity bit. Figure 113 shows the transmitter
data formats.
Parity is enabled by setting Port 3 Mode Register bit 7 to 1. If even parity
is required, PARITY mode should be disabled (P3M bit 7 reset to 0), and
software must modify the data to include even parity.
Because the transmitter can be overwritten, the user is able to generate a
break signal. This is done by writing null characters to the transmitter
buffer (SIO Register [F0h]) at a rate that does not allow the stop bits to be
output. Each time the SIO Register is loaded, the divide-by-16 counter is
resynchronized and a new start bit is output followed by data.
Serial Input/Output
UM001602-0904