Z86E3016PSG Datasheet, PDF (319/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
301
Flag
C
Z
S
V
D
H
Description
Set if the bit rotated from the least significant bit position was 1
(i.e., bit 0 was 1).
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b (Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECh will be used as the
destination operand in the Op Code.
E
dst
Example
If the contents of Register C6h are DDh (11011101b) and the C Flag is
reset, the statement:
RRC C6h
Op Code: C0 C6
leaves the value 6Eh (01101110b) in register C6h. The C and V Flags are
set, and the Z and S flags are cleared.
Example
If the contents of Register 2Ch are EDh, the contents of Register EDh is ←
(00000000b), and the C Flag is reset, the statement:
RRC @2Ch
Op Code: C1 2C
leaves the value 02h (00000010b) in Register EDh. The C, Z, S, and V
Flags are reset.
UM001602-0904
Instruction Description