Z86E3016PSG Datasheet, PDF (185/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
167
Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
0 P30 Input and P37 = Output
1 P30 Serial In and P37 = Serial Out
Figure 106. Port 3 Mode Register and Bit-Rate Generation
The divide chain that generates the bit rate is shown in Figure 107. The bit
rate is given by the following equation:
Bit Rate = XTAL Frequency ÷ (2 x 4 x p x t x 16)
where p and t are the initial values in Prescaler0 and Counter/Timer0,
respectively. The final divide-by-16 is required because T0 runs at 16
times the bit rate in order to synchronize on the incoming data.
f_XTAL
÷2
÷4
P
t
PRE0
T0
Figure 107. Bit Rate Divide Chain
÷16
Bit Rate
Clock
To configure the Z8^® CPU for a specific bit rate, appropriate values as
determined by the above equation must be loaded into registers PRE0
(F5h) and T0 (F4h). PRE0 also controls the counting mode for T0 and
should therefore be set to CONTINUOUS mode (D0 = 1).
For example, given an input clock frequency (XTAL) of 11.9808 MHz
and a selected bit rate of 1200 bits per second, the equation is satisfied by
UM001602-0904
Serial Input/Output