Z86E3016PSG Datasheet, PDF (87/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
69
memory. The input buffers can be Schmitt-triggered, level- shifted, or a
single-point buffer. In some cases, the output buffers can be globally pro-
grammed as either push–pull or open-drain. Low-EMI output buffers can
be globally programmed by software, as an OTP program option, or as a
ROM Mask Option. In some cases, the Z8^® MCU can have autolatches
hardwired to the inputs. Please refer to specific product specifications for
exact input/output buffer-type features available (Figures 32 and 33).
Register F8h (P01M)
Port 0–1 Mode Register (P01M)
(Write-Only)
D7 D6
D1 D0
P04–P07 Mode
00 = Output
01 = Input
1X = A12–A15
P00–P03 Mode
00 = Output
01 = Input
1X = A8–A11
Figure 32. Port 0 I/O Operation
Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D2
0 P32 = Input
P35 = Output
1 P32 = DAV0/RDY0
P35 = RDY0/DAV0
Figure 33. Port 0 Handshake Operation
UM001602-0904
I/O Ports