Z86E3016PSG Datasheet, PDF (145/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
127
OSC
Internal
Clock
÷2
P3₆
T_OUT
TMR D₆
TMR D₇
Figure 79. Internal Clock Output Through T_OUT
T_IN Modes
The Timer Mode Register TMR (F1h; see Figure 80) is used in conjunc-
tion with the Prescaler Register PRE1 (F3h; see Figure 81) to configure
P31 as T_IN. T_IN is used in conjunction with T1 in one of four modes:
• External Clock Input
• Gated Internal Clock
• Triggered Internal Clock
• Retriggerable Internal Clock
The T_IN mode is restricted for use with timer 1 only. To enable the T_IN
mode selected (via TMR bits 4- 5), bit 1 of PRE1 must be set to 0.
The counter/timer clock source must be configured for external by setting
the PRE1 Register bit 2 to 1. The Timer Mode Register bit 5 and bit 4 can
then be used to select the appropriate T_IN operation.
UM001602-0904
Counters and Timers