Z86E3016PSG Datasheet, PDF (160/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
142
clocks earlier, due to the synchronizing flip-flops shown in Figures 92 and
93.
At sample time the request is transferred to the second flip-flop in
Figure 94, that drives the interrupt mask and priority logic. When an inter-
rupt cycle occurs, this flip-flop will be reset only for the highest priority
level that is enabled.
The user has direct access to the second flip-flop by reading and writing
the IRQ Register. IRQ is read by specifying it as the source register of an
instruction and written by specifying it as the destination register.
Q
IRQ0–IRQ5
To Mask
Q
and
Priority
Logic
S
Sample
Clock
R
R
From
Priority
Logic
Figure 94. IRQ Register Logic
Interrupts
UM001602-0904