Z86E3016PSG Datasheet, PDF (85/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
67
OEN
PIN
OUT
TTL Level Shifter
IN
Figure 31. Port 0 Configuration with TTL Level Shifter
Read/Write Operations
In the nibble I/0 Mode, Port 0 is accessed as general-purpose register P0
(00h) with ERF Bank set to 0. The port is written by specifying P0 as an
instruction's destination register. Writing to the port causes data to be
stored in the port's output register.
The port is read by specifying P0 as the source register of an instruction.
When an output nibble is read, data on the external pins is returned.
Under normal loading conditions this is equivalent to reading the output
register. However, for Port 0 outputs defined as open–drain, the data
returned is the value forced on the output by the external system. This
may not be the same as the data in the output register. Reading a nibble
defined as input also returns data on the external pins. However, input bits
UM001602-0904
I/O Ports