Z86E3016PSG Datasheet, PDF (149/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
131
OSC
÷2
Internal
Clock
T_IN
P3₁
Trigger
DD
Edge
Trigger
TMR
D_{5 =} 1
÷4
PRE1 T1
IRQ₅
TMR
D₅–D_{4 =} 11
IRQ₂
Figure 84. Triggered Clock Mode
Retriggerable Input Mode
The T_IN Retriggerable Input Mode (TMR bits 5 and 4 are set to 1) causes
T1 to load and start counting on every occurrence of a High-to-Low tran-
sition on T_IN (see Figure 84). Interrupt request IRQ5 will be generated if
the programmed time interval (determined by T1 prescaler and counter/
timer register initial values) has elapsed because the last High-to-Low
transition on T_IN. In Single-Pass Mode, the end-of-count resets the Enable
Count bit. Subsequent T_IN transitions will not cause T1 to load and start
counting until software sets the Enable Count bit again. In Continuous
Mode, counting continues once T1 is triggered until software resets the
Enable Count bit. When enabled, each High-to-Low T_IN transition causes
T1 to reload and restart counting. Interrupt request IRQ5 is generated on
every end-of-count.
UM001602-0904
Counters and Timers