Z86E3016PSG Datasheet, PDF (263/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
245
Decrement
DEC dst
Instruction Format
OPC
dst
Cycles
6
6
OPC
(Hex)
00
01
Address
Mode dst
R
IR
Operation
dst ← dst–1
The contents of the destination operand are decremented by one.
Flag
C
Z
S
V
D
H
Description
Unaffected
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set (negative); cleared otherwise
Set if arithmetic overflow occurs; cleared otherwise
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b (Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECh will be used as the
destination operand in the Op Code.
E
dst
Example
If Working Register R10 contains 2A%, the statement:
DEC R10
Op Code: 00 EA
UM001602-0904
Instruction Description