Z86E3016PSG Datasheet, PDF (187/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
169
Register F5h
Prescalar 0 Register (PRE0)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 = T₀ Single Pass
1 = T₀ Modulo-n
(Range: 1-64 decimal, 01h–00h)
(Range: 1-64)
Figure 108. Prescaler 0 Register Bit-Rate Generation
The bit rate generator is started by setting the Timer Mode Register
(TMR) (F1h) bit 1 and bit 0 both to 1 (see Figure 109). This transfers the
contents of the Prescaler 0 Register and Counter/Timer0 Register to their
corresponding down counters. In addition, counting is enabled so that
UART operations begin.
Register F1h
Timer Mode Register (TMR)
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
0 = No Function
1 = Load T₀
0 = Disable T₀ Count
1 = Enable T₀ Count
Figure 109. Timer Mode Register Bit Rate Generation
UM001602-0904
Serial Input/Output