Z86E3016PSG Datasheet, PDF (209/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
191
Please note that if Port 0 is configured as A15–A8 and the stack is
selected as internal, any stack operation will cause the contents in register
FEh to be displayed on Port 0.
Register F8h (P01M)
Port 0–1 Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Z8 Stack Selection
0 = External
1 = Internal
Figure 124. Z8 Stack Selection
Data Memory
The two Z8 external memory spaces, data and program, are addressed as
two separate spaces of up to 64 KB each. External program memory and
external data memory are logically selected by the data memory select
output (DM). DM is made available on Port 3, bit 4 (P34) by setting bit 4
and bit 3 in the Port 3 Mode Register (F7h) to 10 or 01 (see Figure 125).
DM is active Low during the execution of the LDE, LDEI instructions,
and High for the execution of program instructions. DM is also active
Low during the execution of CALL, POP, PUSH, RET and IRET instruc-
tions if the stack resides in external data memory. After a RESET, DM is
not selected.
UM001602-0904
External Interface