Z86E3016PSG Datasheet, PDF (200/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
182
Receive Character Available and Overrun
When a complete data stream is received, an interrupt is generated and the
RxCharAvail bit in the SCON Register is set. Bit 4 in the SCON Register
is for enabling or disabling the RxCharAvail interrupt. The RxCharAvail
bit is available for interrupt polling purposes and is reset when the
RxBUF Register is read. RxCharAvail is generated in both master and
slave modes. While in slave mode, if the RxBUF is not read before the
next data stream is received and loaded into the RxBUF Register, Receive
Character Overrun (RxCharOverrun) occurs. Because there is no require-
ment for clock control in slave mode, bit D1 in the SPI Control Register is
used to log any RxCharOverrun (see Figures 118 and 119).
TSK
SK
3
SS
4
D0
DI
Serial Input/Output
2
1
5
Figure 118. SPI Timing
UM001602-0904